Field of the Invention and Related Art Statement
The present invention relates to a video-signal time-axis correction apparatus provided for locking synchronizing signals of an externally supplied video-signal in phase onto those prepared within a TV station, for correcting temporal fluctuation of a video-signal reproduced from VTR and for the like.
As for conventional video-signal time-axis correction apparatuses of this kind, a frame synchronizer, a time base corrector (TBC) and the like are well-known. The present invention is intended for simplifying the configuration employing memories of these conventional apparatuses.
First of all, for clarifying difficulties contained in the conventional configuration thereof, the basic operation of these conventional apparatuses will be described hereinafter by referring to FIG. 1.
FIG. 1 is a block diagram showing the basic configuration of the conventional frame synchronizer, TBC and the like. In FIG. 1, an input analog video signal is converted to an input digital video signal through an A-D converter 1, the latter being written in a memory 2. The timings of the conversion in the A-D converter 1 and the writing in the memory 2 are controlled by synchronizing signals separated from the input analog video signal through a synchronizing signal separator 5. On the other hand, the timing of the reading of an output digital video signal from the memory 2 is controlled by standard synchronizing signals supplied through a synchronizing signal reproducer 8, the latter synchronizing signals being prepared in the TV station apart from the former at all. As a result, the correction of nonstandardized time-axis of the input analog video signal can be effected.
Further speaking in detail by referring to FIGS. 2(a) to 2(g), in the synchronizing signal separator 5, writing clear pulses as shown in FIG. 2(b) and writing clock pulses as shown in FIG. 2(c) are generated on the basis of the vertical and the horizontal synchronizing signals and color burst signals contained in the input analog video signal. The writing clear pulses are situated at the timing corresponding to the blanking intervals of the input analog video signal, so as to clear a counter provided in a writing address generator 6 for counting the writing clock pulses at the timing concerned. The writing clock pulses effect the counting-up of thus cleared counter, so as to generate writing addresses for the memory 2 as shown in FIG. 2(d), as well as these pulses are employed as for sampling pulses driving the A-D converter 1.
The writing addresses for the memory 2 are obtained from the input analog video signal as mentioned above, so that, even if any jitter is contained in the input analog video signal, the same jitter is contained in those writing addresses also and hence the input digital video signal can be always written in the memory 2 in a well-regulated situation.
On the other hand, as for the reading-out of the memory 2, reading addresses as shown in FIG. 2(f) are generated in a reading address generator 7 from reading clock pulses and reading clear pulses as shown in FIG. 2(e), which are generated on the basis of vertical and horizontal synchronizing signals and color burst signals contained in a standard synchronizing signal adopted in the TV station.
This reading address generator 7 is operated at the timing quite unrelated to that of the writing address generator 6, at which timing an output digital video signal is read out from the memory 2 as shown in FIG. 2(g).
Consequently, respective timings on input and output sides of the configuration as shown in FIG. 1 can be isolated from each other through the memory. This is the operational principle of the time-axis correction apparatus in general.
It is clarified by investigating the above described operation with regard to the memory that both of the writing and the reading accesses based on respective timings being isolated from each other are required to be simultaneously attained.
For the above simultaneous attainment, the procedure as shown in FIGS. 3(a) to 3(c) has been conventionally adopted. As shown in FIG. 3(c), the access operation of the memory is restricted within one third of the time duration of the above described writing access based on writing clock pulses. This time duration is divided into three sections of one third thereof, one of which sections is fixedly allotted to the actual writing access as indicated by a mark W. The remaining two sections as indicated by marks R.sub.1 and R.sub.2 are allotted to the actual reading access such as one of these remaining sections, that is, R.sub.1 or R.sub.2 can be arbitrarily allotted thereto. As a result, the actual writing access can be necessarily effected within the section indication by the mark W, meanwhile the actual reading access can be effected within one of the remaining sections indicated by the marks R.sub.1 and R.sub.2 in spite of any phase relation between the aforesaid writing access and the aforesaid reading access. In this connection, it is required to select the section indicated by the mark R.sub.1 or R.sub.2 in response to the detected phase relation between the aforesaid writing and reading accesses. A memory address generator 4 is employed for realizing this procedure and hence has a fairly complicated arrangement. Actually, this memory address generator occupies a large part of the configuration of the conventional apparatus of this kind of such as the frame synchronizer.